Michael Kogan freelancer
"Digital ASIC implementation and DFT Consultant"

After 17 years (in 2014) of work at ASIC Design Service companies as Feld Application Engineer, where I gain a lot of experience and technical skills, allowed me to span the very wide range of the Digital IC Implementation (RTL to GDS design, DFT and ATPG) flow in literally every single part of the flow, I decide to work as Freelancer.

My goal:

is to speedup Time to Market of my customers, by providing full range of ASIC Design Implementation Services, include DFT and ATPG, and use my know-how for the customer success.

My Services:

• Physical implementation (layout) of digital IC: full range of RTL to GDS services
• Timing and power analysis and closure
• Design for test solutions (DFT): setup test concept, all kind of DFT insertion (scan chain compresion, core wrapper isolation chain, JTAG, iJTAG ext.), test patterns generation (ATPG) and simulations.
• RTL and Timing Constraint validation
• Synthesis and Logic Equivalence Check
• Ramp up of young engineer, start-up teams on digital IC implementation flow.

For implementation of my servoices I use the following Tools:

• Synthesis: Design Compiler (DC) of Synopsys or Genus of Cadence
• Logic Equivalcence Check: Formality of Synopsys or Conformal LEC of Cadence
• Static Timing Analysis (STA): Prime Time of Synopsys or ETS of Cadence
• Scan Insertion: DFTMax of Synopsys or Genus of Cadence
• ATPG: Tmax (TetraMax) of Synopsys, Modus of Cadence, Tessent(FastScan) of Mentor
• Physical Implementation (RTL to GDS): Innovus(Encounter) of Cadence
• Simulation: VCS of Synopsys, NCsim of Cadence or Vsim(Modelsim) of Mentor

I always ready for new challenge and ramp up myself quickly on new tool available on customer side. To keep my updated I visit various EDA trainings, seminars and fairs.

I like to use my experience to implement your Idea in Silicon, and make your Chip working from the first time.