Short introduction of Michael Kogan work experience



Digital ASIC Implementation and DFT Consultant
Freelancer Jan. 2014 - now
Munich, Germany



Provide the following Services for various international customers across Europe, North America and Israel:
  • Layout (physical implementation/place & route) of digital IC: RTL to GDSII
  • Timing and power analysis and closure
  • Design for test solutions (DFT): setup test concept, all kind of DFT insertion (scan chain compresion, core wrapper isolation chain, JTAG, iJTAG ext.), test patterns generation and simulations.
  • RTL and Timing Constraint validation
  • Synthesis and Logic Equivalence Check
  • Ramp up of young engineer, start-up teams on digital IC implementation flow.

Project Examples: Layout / DFT



Technical Expert of Digital IC Design and ASIC back-end
Matis-Deutschland Feb. 2011 - Dec. 2013
Munich, Germany

Onsite and remote support of a customers from Automotive, Aerospace and Defence markets.
Synthesis, STA, DFT, Floorplan, layout of complex device at High Radiation(Space) technology, supervision of physical implementation by subcontractors.

ASIC and FPGA Designer at Healthcare division
Siemens AG Oct. 2009 - Jan. 2011
Erlangen, Germany

  • Design of complex FPGA for Medical device chip
  • VHDL coding from spec
  • RTL verification and optimization for Xilinx Virtex5 technology
  • Formal Verification and RTL quality check
  • Adaptation of an old code to new spec and technology


DFT Consultant (freelancer)
Micronas GmbH Feb. 2009 - Sept. 2009
Munich, Germany

  • Testability analysis of complex Digital TV design
  • Stuck-at and at-Speed Automatic Test Pattern Generation (ATPG)
  • Test coverage improves and test vector amount reduction


Lead Services Application Engineer
Cadence Design Systems May. 2004 - Jan. 2009
Munich, Germany

  • Project management: schedule and Statement of Work (SOW) definition and monitoring
  • Technical lead of flat (one man), and hierarchical (multi engineers) designs
  • Work in international teams (3-6 engineers) with colleagues from Russia, Israel, China, India and Europe
  • Physical implementation: RTL-synthesis trough Place and Route Layout implementation to Physical Verification and Tape-out to foundry of high-performance and ultra-low-power SOC devices at 180nm - 65nm technologies, for various customers from Russia, Israel and Europe
  • Design for Test (DFT):Setup test concept for a complex designs, Scan-chains insertion with and without compression logic,Boundary Scan insertion and test vectors generation, Power domain aware scan-chain insertion and test vectors generation, Automatic Test Pattern Generation (ATPG) for stuck-at, at-speed, Iddq
  • Customer relationship: Methodology and design environment setup, Ramp-up customer team to work with Cadence tools on IC digital design implementation, know-how transfer
  • Trainings for both customer and internal teams on: RTL Compiler, SOC Encounter, Encounter Test, Conformal Logic Equivalence Check, with cooperation of Education Department of Cadence.

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Older positions can be seen in full CV at PDF format